1. Field of the Invention
The present invention relates to a semiconductor device and its manufacturing method, and more specifically to a semiconductor device provided with a multiple-state ROM (Read Only Memory) for storing multiple-state level data and its manufacturing method.
2. Description of the Prior Art
Conventionally, in a memory cell array of masked ROM (read only semiconductor memory device), a plurality of memory cells composed of MOS transistors are arranged into a matrix pattern; gates of the memory cells are connected to a plurality of word lines extending in the row direction, respectively; and source and drain diffusion regions are connected to a plurality of bit lines extending in the column direction, respectively. FIG. 1 is a circuit diagram thereof, in which the memory cells are arranged into a matrix pattern; each of the gates of the memory cells is connected to each of a plurality of word lines W1, W2, . . . ; and each of the source and drain diffusion regions is connected to each of a plurality of bit lines B1, B2, . . . Further, the memory cells are of depletion type transistors a to d and of enhancement type transistors (reference symbols omitted).
Now, when data stored in the memory cell a is required to be read, the word line W2 connected to the memory cell a is set to a low level (e.g., 0 V) and all the word lines W1, W3 and W4 other than the word line W2 are set to a high voltage (e.g., 5 V); and further the bit line B1 connected to the memory cell a is set to a high voltage (e.g., 2 V). Under these conditions, if current flows through the memory cell, the memory cell a is determined to be a depletion type transistor; and if no current flows therethrough, the memory cell a is determined to be an enhancement type transistor. In the conventional masked ROM, data of "0" and "1" can be discriminated on the basis of whether the memory cell is of depletion type or enhancement type.
To obtain the transistor of depletion type, ions are implanted appropriately into a channel region formed under a gate electrode and between source and drain regions. In the masked ROM of this structure, however, with the advance of the memory capacity, since the parasitic capacitance of the bit lines increases with increasing number of memory cells connected to the bit lines the data read speed decreases. To overcome this problem, a ROM for reducing the parasitic capacitance of the bit lines for improvement of the data read speed has been proposed, in which the bit lines are divided into a main bit line group of a long wiring length and a subsidiary bit line group of a short wiring length; the memory cells are accommodated in a plurality of banks, respectively; and the memory cells of each bank are connected to the subsidiary bit lines. In the conventional ROM as described above, however, since one memory cell can store only onebit data of "0" or "1", when a large-capacity memory is required to be realized, there exists such a drawback that the chip size increases inevitably.
To overcome this problem, another method has been proposed such that 2 or more bit data can be stored in one memory cell to reduce the chip size, which is referred to as a multiple-state ROM. In the multiple-state ROM, the channel conductances of the respective memory cell transistors are set to a plurality of predetermined different values by changing the gate length and/or width of the memory cell transistors. Or the threshold voltages of the memory cell transistors are set to a plurality of different values by controlling the implantation rate of ions into the channel region formed under the gate electrode and between the source and drain regions. In order to control the implantation rate, however, it has been necessary to implant ions several times.
Here, a prior art method of changing the threshold voltage of the transistor will be explained hereinbelow with reference to FIGS. 2 to 4, which is disclosed in Japanese Published Unexamined (Kokai) Patent Application No. 3-185758.
FIG. 2 is a plane view showing a transistor formed on a semiconductor substrate;
FIG. 3 is a cross-sectional view taken along a line A-A' in FIG. 2; and FIG. 4 is a graphical representation showing the characteristics of dependency of the threshold voltage upon the overlap rate of the transistor gate portion with an ion implantation opening formed on a photoresist. As shown in FIG. 2, a source region 41 and a drain region 42 are arranged at an interval on a principal plane of a p-type silicon semiconductor substrate 1. Further, as shown in FIG. 3, a gate electrode 30 is formed on a gate oxide film 20 over and between the source and drain regions. A field oxide film 90 is formed outside of the active area. In the transistor formed as described above, to obtain the transistor having a predetermined threshold voltage, a photo mask 80 formed with a mask pattern 50 which opens over a gate electrode 30 of the transistor is arranged over the semiconductor substrate 1. Here, an end portion (on the left side) of the mask pattern 50 (the opening 60 in FIG. 2) along the longitudinal direction (the right and left direction in FIG. 2) of the gate electrode 30 is apart by a distance X from end portions (on the left sides) of the source region 41 or drain region 42. On the semiconductor substrate 1, a photoresist 70 is formed, an implantation opening 60 for determining the threshold voltage thereof is formed in the photoresist 70 so as to correspond to the mask pattern 50. Further, ions are implanted at a predetermined implantation rate through the formed opening 60. In this case, a threshold voltage can be determined by controlling the ion concentration implanted into the channel region between the source and drain regions 41 and 42 of the transistor. That is, the threshold voltage thereof can be decided on the basis of the distance X. In this method, the openings 60 of all the transistors can be formed by only one photolithography and further ions can be implanted to all the transistors simultaneously.
In the above-mentioned structure, however, when the threshold voltages are required to be set to four states of 0.5, 2.3, 4.1 and 5.9 V, for instance, the maximum allowable voltage margin is 1.8 V. In the current situation, however, since there inevitably exists an alignment offset (error) of about 0.2 .mu.m in the photoresist, if the distance X is offset by 0.2 .mu.m as an error, the threshold voltage differs as high as about 2.5 V, as shown in FIG. 4. In other words, in the case where the four states are required to be formed by changing the effective channel width of the transistors in accordance with this method, it has been necessary to increase the channel width sufficiently wide to such an extent that the channel width dispersion due to the mask alignment error can be disregarded, for instance to such an extent that W/4&gt;&gt;0.2 .mu.m can be satisfied (where W is a channel width), with the result that the cell size itself has been inevitably increased.
In summary, in the conventional method, when the multiple-state ROM of small cells is formed, since the channel width disperses due to the alignment error of the photoresist, the channel conductance gm inevitably changes, thus causing a problem in that the threshold voltage disperses. As a result, in the prior art multiple-state ROM, it has been difficult to increase the integration rate and the capacity of the multiple-state ROM.